`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:03:10 05/04/2013 
// Design Name: 
// Module Name:    Processor 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Processor #(parameter N = 4) (
    input pop_data,
    input [7 : 0] data_in,
    input read,
	 input clk,
	 input rst,
    input [1 : 0] read_addr_in,
    output [N - 1 : 0] data_out
    );
	 
	 // Register insantiation
	wire SUM;
	wire CMP;
	wire MUL;
	wire LDR;
	
	wire [3:0] ID_to_RS_Data;
	wire [1:0] ID_to_RS_Addr_In;
	wire write_to_reg;
	
	wire [3:0] RS_to_ALU_REGA;
	wire [3:0] RS_to_ALU_REGB;
	wire [3:0] RS_to_SevSeg_Data_Out;
	wire [1:0] ID_to_RS_DestAddr;
	wire [1:0] ID_to_RS_srcASel;
	wire [1:0] ID_to_RS_srcBSel;
	
	wire [7:0] ALU_to_RS_Data_Out;
	 
	 //Module instantiation
	 
	 ALU alu (.SUM(SUM),
				 .CMP(CMP),
				 .MUL(MUL),
				 .REGA(RS_to_ALU_REGA),
				 .REGB(RS_to_ALU_REGB),
				 .d_out(ALU_to_RS_Data_Out)
				 );
				 
	 InstructionDecoder ID (.pop_data(pop_data),
									.data_in(data_in),
									.data_out(ID_to_RS_Data),
									.addr_out(ID_to_RS_Addr_In),
									.ldr(LDR),
									.sum(SUM),
									.mul(MUL),
									.cmp(CMP),
									.write_to_reg(write_to_reg)
									);
	
	 RegisterSet RS (.data_in(ID_to_RS_Data),
						  .addr_in(ID_to_RS_Addr_In),
						  .ldr(LDR),
						  .clk(clk),
						  .rst(rst),
						  .alu_data_in(ALU_to_RS_Data_Out),
						  .read(read),
						  .sev_seg_read_addr(read_addr_in),
						  .REGA(RS_to_ALU_REGA),
						  .REGB(RS_to_ALU_REGB),
						  .data_out(RS_to_SevSeg_Data_Out),
						  .write_to_reg(write_to_reg)
						  );
									


	
	// Code
	assign data_out = RS_to_SevSeg_Data_Out;
endmodule
